Although die thickness is currently the primary challenge, semiconductor companies are exploring silicon wafer thicknesses below 50 µm, potentially reaching the capability of blade dicing. Issues such ...

Ferroelectrics at the nanoscale exhibit a wealth of polar and sometimes swirling (chiral) electromagnetic textures that not ...

Bernardette Kunert, scientific director at imec, commented, “Over the past years, imec has pioneered nano-ridge engineering, a technique that builds on SAG and ART to grow low-defectivity III-V ...